Lesson 1 of 5

Switches, XOR and an active-low key

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// Switches to LEDs, one XOR gate and an active-low key. // Port names from Terasic's System Builder .qsf, which gives each bit its FPGA pin. module top ( input [9:0] SW, // 10 slide switches, up = 1 input [1:0] KEY, // 2 push buttons, 0 while pressed output [9:0] LEDR ); assign LEDR[7:0] = SW[7:0]; // SW7-SW0 straight to the LEDs above them assign LEDR[8] = SW[8] ^ SW[9]; // lit when exactly one of SW8 and SW9 is up assign LEDR[9] = ~KEY[0]; // a key reads 0 when pressed, so invert it endmodule

Stopped · Your code isn't running yet. Until you press Run, the board runs the program already on it.

Nothing printed yet. Press Run.

SW7-SW0 light the LEDs above them, LEDR8 shows SW8 XOR SW9, and LEDR9 lights while you hold KEY0. A key reads 0 when pressed, so the design inverts it.

Wires and gates with assign
Active-low inputs: invert KEY
Flip switches and press KEY0 while it runs

iynk runs your Verilog as a behavioural model, cycle by cycle on the board clock. It does not synthesise, place or route: no timing, no LUT counts.

Pin	Connects to	What it does
`SW8`	FPGA pin B14 (SW[8])	Input A of the XOR
`KEY0`	U14 Schmitt buffer → FPGA pin B8 (KEY[0])	0 while pressed
`LEDR9`	FPGA pin B11 (LEDR[9])	Lit while KEY0 is held

Wire it in

Sensors and actuators this board drives, with the real connections.

All 7 parts on the Terasic DE10-Lite page

Switches, XOR and an active-low key

Try it yourself

Serial monitor

Checks

Break it

Inputs

Wire it in

Switches, XOR and an active-low key

Try it yourself

Serial monitor

Checks

Break it

Inputs

Wire it in