Lesson 3 of 5

Count key presses, hold to clear

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// Count KEY0 presses on the LEDs; hold KEY1 for a second to clear. module top #( parameter CLK_HZ = 50_000_000 ) ( input MAX10_CLK1_50, input [1:0] KEY, // 0 while pressed, debounced on the board output [9:0] LEDR ); // 1. Synchronise: two flip-flops bring each key onto our clock. reg [1:0] k0 = 2'b11; reg [1:0] k1 = 2'b11; always @(posedge MAX10_CLK1_50) begin k0 <= {k0[0], KEY[0]}; k1 <= {k1[0], KEY[1]}; end // 2. Edge: a pulse one clock long when KEY0 goes from 1 to 0. wire press = k0[1] & ~k0[0]; // 3. Hold: count cycles while KEY1 is down; a full second clears. localparam HOLD = CLK_HZ; reg [31:0] held = 0; always @(posedge MAX10_CLK1_50) begin if (k1[1]) held <= 0; else if (held != HOLD) held <= held + 1; end wire clear = (held == HOLD - 1); // 4. Count the presses; a clear wins. reg [9:0] count = 0; always @(posedge MAX10_CLK1_50) begin if (clear) count <= 0; else if (press) count <= count + 1; end assign LEDR = count; endmodule

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Each press of KEY0 adds one to a binary number on the LEDs. A tap on KEY1 does nothing; holding it for a second clears the count.

Synchronise and find the falling edge
Tell a tap from a hold by counting cycles
Keys debounced on the board

iynk runs your Verilog as a behavioural model, cycle by cycle on the board clock. It does not synthesise, place or route: no timing, no LUT counts.

Pin	Connects to	What it does
`KEY0`	U14 → PIN_B8 (KEY[0])	Each press adds one
`KEY1`	U14 → PIN_A7 (KEY[1])	Hold for a second to clear
`LEDR0`	PIN_A8 (LEDR[0])	Bit 0 of the count

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Sensors and actuators this board drives, with the real connections.

All 7 parts on the Terasic DE10-Lite page

Count key presses, hold to clear

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Serial monitor

Checks

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Inputs

Wire it in

Count key presses, hold to clear

Try it yourself

Serial monitor

Checks

Break it

Inputs

Wire it in