Lesson 2 of 5

Blink from the 50 MHz clock

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// Blink: count clock cycles and flip LEDR0 every half period. module top #( parameter CLK_HZ = 50_000_000, // the board clock: cycles per second parameter BLINK_HZ = 2 ) ( input MAX10_CLK1_50, output reg [9:0] LEDR ); // Clock cycles in half a blink. localparam HALF = CLK_HZ / (2 * BLINK_HZ); reg [31:0] count = 0; initial LEDR = 10'b0; always @(posedge MAX10_CLK1_50) begin if (count == HALF - 1) begin count <= 0; LEDR[0] <= ~LEDR[0]; // flip LEDR0 if (LEDR[0]) LEDR[9:6] <= LEDR[9:6] + 1; // LEDR0 is about to go off: one more blink end else begin count <= count + 1; end end endmodule

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There is no delay(): LEDR0 blinks because the design counts 50 million clock cycles a second, and LEDR9-LEDR6 count the blinks.

Sequential logic with always @(posedge clk)
Time from counting, not waiting
Set the blink rate with a chip

iynk runs your Verilog as a behavioural model, cycle by cycle on the board clock. It does not synthesise, place or route: no timing, no LUT counts.

Pin	Connects to	What it does
`MAX10_CLK1_50`	CDCE937 (U3) → PIN_P11	Every rising edge updates the registers
`LEDR0`	FPGA pin A8 (LEDR[0])	Changes state every HALF cycles
`LEDR6`	FPGA pin E14 (LEDR[6])	Lowest bit of the blink count

Wire it in

Sensors and actuators this board drives, with the real connections.

All 7 parts on the Terasic DE10-Lite page

Blink from the 50 MHz clock

Try it yourself

Serial monitor

Checks

Break it

Parameters

Wire it in

Blink from the 50 MHz clock

Try it yourself

Serial monitor

Checks

Break it

Parameters

Wire it in