Lesson 1 of 5

Logic gates from switches

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// Logic gates: four LEDs show what two switches make. // The port map (Vivado's XDC file) puts sw on the 16 switches and led on the 16 LEDs. module top ( input [15:0] sw, // the 16 slide switches, up = 1 output [15:0] led // the 16 green LEDs, 1 = on ); assign led[0] = sw[0] & sw[1]; // AND: lit when both are up assign led[1] = sw[0] | sw[1]; // OR: lit when either is up assign led[2] = sw[0] ^ sw[1]; // XOR: lit when exactly one is up assign led[3] = ~sw[0]; // NOT: lit while SW0 is down // LD4-LD15 simply follow their switches. assign led[15:4] = sw[15:4]; endmodule

Stopped · Your code isn't running yet. Until you press Run, the board runs the program already on it.

Nothing printed yet. Press Run.

Your first FPGA design is pure logic: four LEDs show AND, OR, XOR and NOT of the two right-hand switches, and the other twelve LEDs copy their switches.

Combinational logic with assign
The port map is your XDC file
Flip the switches on the board while it runs

iynk runs your Verilog as a behavioural model, cycle by cycle on the board clock. It does not synthesise, place or route: no timing, no LUT counts.

Pin	Connects to	What it does
`SW0`	FPGA pin V17 (sw[0])	Input A of every gate
`SW1`	FPGA pin V16 (sw[1])	Input B
`LD0`	FPGA pin U16 (led[0])	Shows A AND B

Wire it in

Sensors and actuators this board drives, with the real connections.

All 5 parts on the Digilent Basys 3 page

Logic gates from switches

Try it yourself

Serial monitor

Checks

Break it

Inputs

Wire it in

Logic gates from switches

Try it yourself

Serial monitor

Checks

Break it

Inputs

Wire it in