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Stopped · Your code isn't running yet. Until you press Run, the board runs the program already on it.
Nothing printed yet. Press Run.
Not checked yet
Run your code to check it. The checks replay a fixed script on a virtual clock, so the same code always gets the same result.
Each fault really happens in the simulation. Trigger one, watch the figure, then read why.
Play the world: press, slide and turn the parts while the code runs.
Change a value here or click a chip in the code.
Show the 16 switches as four hex digits. The digits share their segment wires, so the design lights them one at a time, fast enough that you see all four.
iynk runs your Verilog as a behavioural model, cycle by cycle on the board clock. It does not synthesise, place or route: no timing, no LUT counts.
| Pin | Connects to | What it does |
|---|---|---|
CA | FPGA pin W7 → 100 Ω → segment a of every digit | 0 lights segment a |
AN0 | FPGA pin U2 → PNP → the right digit's anode | 0 turns on the rightmost digit |
SW0 | FPGA pin V17 (sw[0]) | Bit 0 of the right digit |
Sensors and actuators this board drives, with the real connections.