Lesson 3 of 5

Count button presses

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// Count BTNC presses on the LEDs; BTNU clears the count. module top #( parameter CLK_HZ = 100_000_000 ) ( input clk, input btnC, // count: 1 while pressed input btnU, // clear output [15:0] led ); // Clock cycles a new button level must hold before we believe it. localparam SETTLE = CLK_HZ / 1000 * 10; // 1. Synchronise: two flip-flops bring btnC onto our clock. reg [1:0] sync = 2'b00; always @(posedge clk) sync <= {sync[0], btnC}; // 2. Debounce: follow the button only once it has been steady for SETTLE cycles. reg clean = 1'b0; reg [31:0] held = 0; always @(posedge clk) begin if (sync[1] == clean) held <= 0; else if (held == SETTLE - 1) begin clean <= sync[1]; held <= 0; end else held <= held + 1; end // 3. Edge: a pulse one clock long when the clean level goes from 0 to 1. reg was = 1'b0; always @(posedge clk) was <= clean; wire press = clean & ~was; // 4. Count the pulses; BTNU wins. reg [15:0] count = 0; always @(posedge clk) begin if (btnU) count <= 0; else if (press) count <= count + 1; end assign led = count; endmodule

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Each press of BTNC adds one to a binary number on the LEDs and BTNU clears it. Real buttons bounce, so the design cleans the signal up first.

Synchronise, debounce, find the edge
See why a bouncing contact counts twice
Change the settle time

iynk runs your Verilog as a behavioural model, cycle by cycle on the board clock. It does not synthesise, place or route: no timing, no LUT counts.

Pin	Connects to	What it does
`BTNC`	FPGA pin U18 (btnC)	Each press adds one
`BTNU`	FPGA pin T18 (btnU)	Clears the count
`LD0`	FPGA pin U16 (led[0])	Bit 0 of the count

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Sensors and actuators this board drives, with the real connections.

All 5 parts on the Digilent Basys 3 page

Count button presses

Try it yourself

Serial monitor

Checks

Break it

Inputs

Parameters

Wire it in

Count button presses

Try it yourself

Serial monitor

Checks

Break it

Inputs

Parameters

Wire it in